Embodiments of the present invention relate generally to semiconductor device fabrication, and more specifically, to detecting defects that form on the backside of a wafer during a wafer manufacturing process of an integrated circuit or semiconductor die and lead to chip cracking.
Bonding and assembly of a semiconductor die to a semiconductor chip package substrate during chip packaging is one aspect in which defects can arise during a wafer manufacturing process of a die. In a typical bonding and assembly process of a semiconductor die to a semiconductor chip package substrate, solder bumps are attached to respective bond pads formed on the die. The semiconductor die is then placed onto the semiconductor chip package substrate. A reflow is performed to join the solder bumps on the semiconductor die to respective bond pads on the semiconductor chip package substrate. Typically, there is a high degree of mismatch between the coefficients of thermal expansion (CTE) between the semiconductor die and the semiconductor chip package substrate. The mismatch of CTE results in the formation of large strains that cause thermal stresses to develop about the solder bumps and the semiconductor die during thermal exposures. In particular, during the semiconductor die-join and cool-down, the mismatch of CTE between the semiconductor die and the semiconductor chip package substrate results in warpage of the semiconductor die and semiconductor chip package substrate. This warpage creates tensile stress on the backside of the semiconductor die. Due to the brittle nature of silicon, any defect on the backside of the semiconductor die makes it very sensitive to this tensile stress. As a result, the semiconductor die may fracture or crack.
Any fractures or cracks that arise during the bonding and assembly of a semiconductor die with a semiconductor chip package substrate via the solder bumps may be further exasperated during a subsequent underfilling process in which the under-chip space between the die and the substrate is filled with a non-conductive “underfill”. The underfill protects the solder bumps from moisture or other environmental hazards, and provides additional mechanical strength to the assembly of the semiconductor die to the semiconductor chip package substrate. However, like the bonding and assembly of a semiconductor die to a semiconductor chip package substrate via the solder bumps, the defects in the backside of the semiconductor die can become further stressed during the underfilling process.
In a typical underfilling process, a cure is performed to join the underfill material with the semiconductor die, the semiconductor chip package substrate and the solder bumps. The mismatch between the CTEs between the underfill material, the semiconductor die, the semiconductor chip package substrate and the solder bumps results in further thermal stresses on the backside of the semiconductor die. As a result, during the join and cool-down of the underfill material, the mismatch of CTE between the semiconductor die, the underfill material and the semiconductor chip package substrate results in warpage of the semiconductor die and semiconductor chip package substrate. This warpage creates tensile stress on the backside of the semiconductor die. Due to the brittle nature of silicon, any defect on the backside of the semiconductor die makes it very sensitive to this tensile stress. As a result, the semiconductor die may fracture or crack.
Since a typical wafer manufacturing process has a multitude of operations, it is conceivable that each of these operations can create a defect on the backside of a wafer that can lead to fractures or cracks in the semiconductors dies that are fabricated in the process. These defects can have an effect on the reliability and yield of the semiconductor die fabricated from such a wafer manufacturing process. Semiconductor manufacturers can utilize defect evaluation methods during the wafer manufacturing process in order to mitigate the effect that defects in the backside of the wafer can have on the reliability and yield of a semiconductor die, but these methods are cumbersome and generally not adept at distinguishing cosmetic defects (e.g., scratches, discolorations, etc.) that occur in large numbers on the backside of the wafers during the wafer manufacturing process from critical defects that lead to fractures and cracks in the die.